65nm cmos standard cell CS200 asic series description features high integration ? ransistor of 30?0nm gate length (itrs road map 65nm) 12-layer fine pitch, copper wiring, and low-k insulating material techniques maximum 180 million gates, nearly twice that of 90nm technology 50% reduction in sram cell size 30% increase in performance over 90nm ? ow power consumption/low leakage current i/o with pad structure with fine pad pitch technology for chip size reduction high-speed library and low-power library available high speed: CS200hp ? ow leak: CS200l higher performance, gate propagation delay tpd = 4.4ps (@1.2v, inverter, and f/o = 1, CS200hp) compiled memory macros: 1t and 6t srams, and rom ? pplication specific ips computational cores: arm7, 9, 11, communication and digital-av dsp mixed signals: wide range of adcs and dacs hsif logics: pci-express, xaui, sata, ddr, usb, hdmi high-speed interface serdes macros (~10gbps data rate) ? ide range of plls: standard to high-speed 1.6ghz standard i/os: lvttl, sstl, hstl, lvds, p-cml ? ide supply voltage (0.80v to 1.30v for core) ? riple vth transistor options ? arious packages available (qfp, fbga, ebga, pbga, fc-bga) design methodology and support methodology in place to support multi-million-gates hierarchical designs ? x cellent design center support at sunnyvale and dallas ? orldwide service organizations for global support CS200 series, 65nm standard cells cmos process technology, addresses the design challenges of the pda and mobile computing market in low power and multi-functionality. it also addresses the need of ultra high performance design in leading-edge networking, server computing, and in complex telecom equipment applications. 65nm technology is available in 300mm fabrication and supports high volume wafer capacity in multiple manufacturing locations. std-tr k std-tr hs-tr hv-tr mo c uhs-tr high performance lineup CS200 high performance lineup CS200hp low power lineup CS200a low power lineup CS200ll leakage current large uhs: ultra high speed, hs: high speed std: standard, ll: low leakage speed fast d- d- d- hs-tr std-tr hv-tr high end server digital consumer cellular phone mobile computing server/ network uhs-tr hs-tr std-tr ll-tr
65nm cmos standard cell fujitsu microelectronics america, inc. corporate headquarters 1250 e. arques avenue, m/s 333, sunnyvale, ca 94085-5401 t el: (800) 866-8608 fax: (408) 737-5999 e-mail: inquiry@fma.fujitsu.com web site: http://us.fujitsu.com/micro ? 2008 fujitsu microelectronics america, inc. all company and product names are trademarks or registered trademarks of their respective owners. printed in the u.s.a. sms-fs-21293-3/2008 memory macros and compilers ? rw sram in 16k x 40-bit max. configuration ? rw sram in 4k x 18-bit max. configuration phase-lock loops analog: up to 3.2ghz dll i/o: high speed interface and conventional ios 2.5v and 3.3v lvcmos p-cml, lvds, sstl, hstl pci express, s-ata, ddr, usb, ddr, hdmi, cdr 3.125gbps xaui, sfi, spi mix-signal macros adc dac 8-bit 54ms/s ? 8-bit 300ks/s 8-bit 110ms/s ? 8-bit 1ms/s 10-bit 1ms/s ? 10-bit 300ks/s 10-bit 33ms/s ? 10-bit 1ms/s 10-bit 1110ms/s ? 10-bit 40ms/s 12-bit 80ms/s dual ? 10-bit 54ms/s 10-bit 110ms/s soc ip cores networking and communication pci-express link & phy, s-ata link & phy, spi4, 10/100/1000 ethernet processors and dsp arm7, 9, 11, arc, tensilica std. bus controllers & bus bridges usb2.0 device/host controller & phy, pci controller, sd/cf card if, i 2 c, uart multimedia access hdmi link & phy, jpeg, ntsc/pal, des/aes encryption memory controllers mobile ddr, ddr2/3, fcram, sdram specifications analog sram logic i/o 6.3mm i/o peripheral peripheral core logic: 4mgate (usage ratio 60%) macro: 2mgate (sram: 0.5m-bit, pll etc.) 65nm compared to 90nm of the same design 60% area reduction 4.9mm analog sram logic
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